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Proceedings Paper

Automated Wafer Flatness Characterization System
Author(s): Stephen Morgan; Zbigniew Sobczak; Gary Lynch; Lee Reid
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Paper Abstract

As VLSI technology pushes toward micrometer range geometries, wafer flatness becomes critical to direct step on wafer projection printing. This paper describes a system that utilizes the automatic focusing capability of a wafer stepper to achieve in situ measurement of wafer flatness. A depth gauge attached to the lens column conveys to the system a voltage analog of column height during exposure of each die. The system then computes locations of isoplanar contour lines on the wafer and plots a topographic map on an X-Y recorder. Any vertical interval between contour lines can be specified between 0.5 and 2 micrometers. A close correlation has been found between interferometric images of wafer flatness and topographic maps produced by the system while attached to a wafer stepper. The chief advantage of the wafer topographic map over the interferometric image is its ability to capture flatness measurements during actual exposure. Also beneficial are tick marks on all contour lines which indicate direction of increasing wafer height. Application of the system will enhance prediction of photolithographic yield, identification of process steps causing wafer deformation and effectiveness of process quality control.

Paper Details

Date Published: 28 July 1981
PDF: 8 pages
Proc. SPIE 0275, Semiconductor Microlithography VI, (28 July 1981); doi: 10.1117/12.931878
Show Author Affiliations
Stephen Morgan, Texas Instruments Incorporated (United States)
Zbigniew Sobczak, Texas Instruments Incorporated (United States)
Gary Lynch, Texas Instruments Incorporated (United States)
Lee Reid, Texas Instruments Incorporated (United States)


Published in SPIE Proceedings Vol. 0275:
Semiconductor Microlithography VI
James W. Dey, Editor(s)

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