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Proceedings Paper

Mask Fabrication Using Electron Beam Exposure System
Author(s): Y. Watakabe; A. Shigetomi; H. Morimoto; T. Kato
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Paper Abstract

This study describes the results of feature size distribution, pattern location accuracy and level to level registration error on chrominum master masks fabricated by EeBES-40. This system has the capability of high speed electron beam blanking at 40MHz, the capacity for large size masks (with 6 inch mask cassette), and the automatic cassette handling system. OEBR-100(PGMA), as the electron beam negative resist, is used for 5 inch and 6 inch chrominum masks. The chrominum etching process is used for both wet and dry plasma technology. Test patterns and 64 K bit memory TEG, as the practical pattern, are used in this study. More than 40 measurements are taken, uniformly distributed over 96 to 112mm square, and the feature size distribution is measured by a laser interferometer X-Y measuring system. Pattern location accuracy and level to level registration error are obtained using EeBES-40 quality assurance programs called MARKET/PLOTMARKET. This program operates by scanning over the resist image of the test pattern, utilizing the normal fiducial mark location hardware. The followinc results are obtained; (1) Feature size distribution within 6 inch mask : ∓0.1 μm (2) Level-to-level registration error2 : less than 0.1 pm High quality masks with about 0.02 defects/cm2 , and rapid throughput of 6 hr./10 masks using the auto-matic 10-cassette handling system are obtained.

Paper Details

Date Published: 28 July 1981
PDF: 8 pages
Proc. SPIE 0275, Semiconductor Microlithography VI, (28 July 1981); doi: 10.1117/12.931875
Show Author Affiliations
Y. Watakabe, Mitsubishi Electric Corporation (Japan)
A. Shigetomi, Computer Development Laboratories Limited (Japan)
H. Morimoto, Computer Development Laboratories Limited (Japan)
T. Kato, Mitsubishi Electric Corporation (Japan)


Published in SPIE Proceedings Vol. 0275:
Semiconductor Microlithography VI
James W. Dey, Editor(s)

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