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Proceedings Paper

Defect inspection strategies for 14 nm semiconductor technology
Author(s): Ralf Buengener
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Paper Abstract

This article presents strategies to overcome the defect inspection challenges expected at the 14 nm technology node: Smaller feature and defect sizes will require very sensitive inspections. At the same time the inspection recipes must be stable against inevitable process variation and potentially high defect density going along with new manufacturing methods for nonplanar transistors (FINFETs). The focus is on existing inspection methods and tools such as brightfield and darkfield optical inspection, e-beam inspection and scanning electron microscopy imaging. Examples from 20 nm technology are shown that can be applied to the next node, including: - Choice of the right type of inspection, based on defect type, - complementary inspections at the same step, each being optimized for certain defect types, - smart use of inspection tool features to extend the usefulness of optical inspection, - use of alternative inspections such as e-beam or advanced process inspection, based on technology maturity, - detection of small systematic defects and random defects, - understanding and overcoming the limitations of inspected area vs. sensitivity and throughput, - monitoring inspection recipe performance.

Paper Details

Date Published: 11 October 2012
PDF: 7 pages
Proc. SPIE 8466, Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors VI, 846607 (11 October 2012); doi: 10.1117/12.928664
Show Author Affiliations
Ralf Buengener, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 8466:
Instrumentation, Metrology, and Standards for Nanomanufacturing, Optics, and Semiconductors VI
Michael T. Postek; Victoria A. Coleman; Ndubuisi G. Orji, Editor(s)

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