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Proceedings Paper

Silicon nanowire arrays using g-line photolithography
Author(s): Rahul Prajesh; Hemant Tholia; Ajay Agarwal
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Paper Abstract

One and two micron wide silicon fin patterns realized using standard g-line UV lithography are oxidized to accomplish nanowires. Simulation results envisage the possibility of silicon nanowire fabrication using top down fabrication approach. Experimental results show the feasibility of the process. SEM imaging was used to characterize the nanowires. Silicon nanowires up to 150 nm are demonstrated by the mentioned top down approach. Silicon consumption from three sides of the fins reduces their cross-sectional geometries. Stress developed during the oxidation of silicon leads to pinch-off in the fins, with aspect ratios <3. This pinch-off divides the fin patterns into two parts vertically; upper part detaches from the lower one and converges into silicon Nanowire, buried in silicon oxide. Simulation and process results for different process temperatures, time and fin aspect ratios are presented in the paper.

Paper Details

Date Published: 15 October 2012
PDF: 6 pages
Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 85492E (15 October 2012); doi: 10.1117/12.927422
Show Author Affiliations
Rahul Prajesh, CSIR-Central Electronics Engineering Research Institute (India)
Hemant Tholia, CSIR-Central Electronics Engineering Research Institute (India)
Univ. of Rajasthan (India)
Ajay Agarwal, CSIR-Central Electronics Engineering Research Institute (India)


Published in SPIE Proceedings Vol. 8549:
16th International Workshop on Physics of Semiconductor Devices
Monica Katiyar; B. Mazhari; Y N Mohapatra, Editor(s)

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