Share Email Print
cover

Proceedings Paper

Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications
Author(s): Vandana Kumari; Manoj Saxena; R. S. Gupta; Mridula Gupta
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper investigates the potential of ISESOV architecture for low-voltage digital applications. A circuit analysis is performed for ISESOV MOSFET in terms of voltage transfer curve (VTC), supply current and noise margin and switching speed. These results are also compared with the ISE, SOV and bulk MOSFET architectures. Further improvement in the characteristic of inverter in terms of VTC and noise margin is observed by incorporating the gate stack architecture. The impact of Dual Material Gate architecture on the inverter performance has been also studied through exhaustive device simulations and it can be concluded that. ISESOV is a promising candidate for future digital applications as compared to ISE, SOV and bulk because it combines the advantages of both ISE and SOV architectures.

Paper Details

Date Published: 15 October 2012
PDF: 6 pages
Proc. SPIE 8549, 16th International Workshop on Physics of Semiconductor Devices, 854905 (15 October 2012); doi: 10.1117/12.925533
Show Author Affiliations
Vandana Kumari, Univ. of Delhi (India)
Manoj Saxena, Univ. of Delhi (India)
R. S. Gupta, Maharaja Agrasen Institute (India)
Mridula Gupta, Univ. of Delhi (India)


Published in SPIE Proceedings Vol. 8549:
16th International Workshop on Physics of Semiconductor Devices
Monica Katiyar; B. Mazhari; Y N Mohapatra, Editor(s)

© SPIE. Terms of Use
Back to Top