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Proceedings Paper

NBTI aware HLS using latches
Author(s): Ramrakesh Jangir; Kalyan Singh Yadav
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Paper Abstract

Time dependent performance degradation due to negative bias thermal instability (NBTI) is one of the most important reliability concerns for deep nano scale regime VLSI circuits. Under worst case NBTI can degrade circuit performance in terms of timing by more than 10% over a period of 3 years. Reliability decisions taken early in system design can bring significant benefits in terms of design quality. The proposed approach deals with use of latches and NBTI aware scheduling of DFG to overcome the timing violations caused by NBTI. The experimental results suggest that it incurs a very low area overhead and no performance penalty. We propose an algorithm to schedule the DFG and show results for some of the common filters like EW and AR.

Paper Details

Date Published: 14 January 2012
PDF: 5 pages
Proc. SPIE 8349, Fourth International Conference on Machine Vision (ICMV 2011): Machine Vision, Image Processing, and Pattern Analysis, 83493M (14 January 2012); doi: 10.1117/12.923771
Show Author Affiliations
Ramrakesh Jangir, Government Polytechnic Hisar (India)
NIIT, Delhi (India)
Kalyan Singh Yadav, Government Polytechnic Hisar (India)
NIIT, Delhi (India)


Published in SPIE Proceedings Vol. 8349:
Fourth International Conference on Machine Vision (ICMV 2011): Machine Vision, Image Processing, and Pattern Analysis
Zhu Zeng; Yuting Li, Editor(s)

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