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Proceedings Paper

Plasma treatment to improve linewidth roughness during gate patterning
Author(s): L. Azarnouche; E. Pargon; K. Menguelti; M. Fouchier; M. Brihoum; R. Ramos; O. Joubert; P. Gouraud; C. Verove
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Paper Abstract

With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an accurate estimation of the CDSEM noise level and extraction of unbiased LWR. In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length, fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H2, He, Ar), and also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H2 that limit carbon redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

Paper Details

Date Published: 17 March 2012
PDF: 11 pages
Proc. SPIE 8328, Advanced Etch Technology for Nanopatterning, 83280H (17 March 2012); doi: 10.1117/12.920314
Show Author Affiliations
L. Azarnouche, STMicroelectronics (France)
E. Pargon, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
K. Menguelti, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
M. Fouchier, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
M. Brihoum, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
R. Ramos, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
O. Joubert, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
P. Gouraud, STMicroelectronics (France)
C. Verove, STMicroelectronics (France)


Published in SPIE Proceedings Vol. 8328:
Advanced Etch Technology for Nanopatterning
Ying Zhang, Editor(s)

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