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Proceedings Paper

Etch challenges for 1xnm NAND flash
Author(s): Myung Kyu Ahn; Woo June Kwon; Chan Sun Hyun; Jin Woong Kim
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Paper Abstract

In recent years, NAND flash technology node has shrunk below to 1x nm patterning with significant progresses of double patterning technology (DPT) and spacer patterning technology (SPT). Plasma etching processes involved in the fabrication of advanced NAND flash device become increasingly challenging. As critical dimensions decrease, controlling of micro-loading and pattern wiggling such as line edge roughness (LER) and line width roughness (LWR) has become key issues. In order to define the fine pattern, plasma etch process regime has been changed to lower pressure and to higher plasma density below sub 40 nm. However, below 20 nm, it seems that control of pressure and plasma density is not enough. In an effort to overcome these huddles, pulsing plasma etch technology has been evaluated for 1x nm node. By using pulsing plasma we have obtained the improvement of etch selectivity and reduction of poly hard mask loss. In this study, we have found that pulse applied etching as well as film stack optimization is remarkably effective to reduce micro-loading and pattern wiggling.

Paper Details

Date Published: 17 March 2012
PDF: 8 pages
Proc. SPIE 8328, Advanced Etch Technology for Nanopatterning, 83280F (17 March 2012); doi: 10.1117/12.920313
Show Author Affiliations
Myung Kyu Ahn, Hynix Semiconductor Inc. (Korea, Republic of)
Woo June Kwon, Hynix Semiconductor Inc. (Korea, Republic of)
Chan Sun Hyun, Hynix Semiconductor Inc. (Korea, Republic of)
Jin Woong Kim, Hynix Semiconductor Inc. (Korea, Republic of)


Published in SPIE Proceedings Vol. 8328:
Advanced Etch Technology for Nanopatterning
Ying Zhang, Editor(s)

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