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Proceedings Paper

Towards new plasma technologies for 22nm gate etch processes and beyond
Author(s): O. Joubert; M. Darnon; G. Cunge; E. Pargon; D. Thibault; C. Petit-Etienne; L. Vallier; N. Posseme; P. Bodart; L. Azarnouche; R. Blanc; M. Haas; M. Brihoum; S. Banna; T. Lill
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Paper Abstract

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

Paper Details

Date Published: 16 March 2012
PDF: 10 pages
Proc. SPIE 8328, Advanced Etch Technology for Nanopatterning, 83280D (16 March 2012); doi: 10.1117/12.920312
Show Author Affiliations
O. Joubert, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
M. Darnon, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
G. Cunge, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
E. Pargon, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
D. Thibault, CEA, LETI, MINATEC (France)
C. Petit-Etienne, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
L. Vallier, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
N. Posseme, CEA, LETI, MINATEC (France)
P. Bodart, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
L. Azarnouche, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
R. Blanc, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
M. Haas, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
M. Brihoum, Lab. des technologies de la Microeléctronique, CNRS (France)
Univ. Joseph Fourier (France)
CEA, LETI, MINATEC (France)
S. Banna, Applied Materials, Inc. (United States)
T. Lill, Applied Materials, Inc. (United States)


Published in SPIE Proceedings Vol. 8328:
Advanced Etch Technology for Nanopatterning
Ying Zhang, Editor(s)

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