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Proceedings Paper

Advanced plasma etch technologies for nanopatterning
Author(s): Rich Wise
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Paper Abstract

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45nm through 14/10nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques such as litho-etch-litho-etch, sidewall image transfer, line/cut mask and self-aligned structures have been implemented to solution required device scaling. Advances in dry plasma etch process control, across wafer uniformity and etch selectivity to both masking materials and have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes such as trilayer etches, aggressive CD shrink techniques, and the extension of resist trim processes have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across design variation, defectivity, profile stability within wafer, within lot, and across tools have been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated Total Patterning Solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. This paper will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Paper Details

Date Published: 16 March 2012
PDF: 10 pages
Proc. SPIE 8328, Advanced Etch Technology for Nanopatterning, 832803 (16 March 2012); doi: 10.1117/12.920307
Show Author Affiliations
Rich Wise, IBM Semiconductor Research and Development Ctr. (United States)


Published in SPIE Proceedings Vol. 8328:
Advanced Etch Technology for Nanopatterning
Ying Zhang, Editor(s)

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