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Proceedings Paper

Extending the DRAM and FLASH memory technologies to 10nm and beyond
Author(s): Kinam Kim; U-In Chung; Youngwoo Park; Jooyoung Lee; Jeongho Yeo; Dongchan Kim
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Paper Abstract

Memory devices such as DRAM and NAND flash will continue to increase their capacity through scaling, which will extend to below the 10nm regime. From a device physics perspective, there are possible solutions for scaling below 10nm. However, the challenges of sub-10nm scaling will come from the productivity. In fact, major challenges for the realization of high density memory devices are lithography and vertical etching of high aspect ratio holes in DRAM and 3D flash memories. Here, status and the direction of DRAM and flash memory scaling technologies will be reviewed with a special focus on the extendibility from not only device physics but also productivity points of view.

Paper Details

Date Published: 13 March 2012
PDF: 11 pages
Proc. SPIE 8326, Optical Microlithography XXV, 832605 (13 March 2012); doi: 10.1117/12.920053
Show Author Affiliations
Kinam Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
U-In Chung, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Youngwoo Park, Samsung Electronics Co., Ltd. (Korea, Republic of)
Jooyoung Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jeongho Yeo, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Dongchan Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)


Published in SPIE Proceedings Vol. 8326:
Optical Microlithography XXV
Will Conley, Editor(s)

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