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Proceedings Paper

Implications of triple patterning for 14nm node design and patterning
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Paper Abstract

The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.

Paper Details

Date Published: 7 March 2012
PDF: 12 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832703 (7 March 2012); doi: 10.1117/12.920028
Show Author Affiliations
Kevin Lucas, Synopsys, Inc. (United States)
Chris Cork, Synopsys, Inc. (France)
Bei Yu, Univ. of Texas (United States)
Gerard Luk-Pat, Synopsys, Inc. (United States)
Ben Painter, Synopsys, Inc. (United States)
David Z. Pan, The Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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