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Proceedings Paper

Yield impacting systematic defects search and management
Author(s): Jing Zhang; Qingxiu Xu; Xin Zhang; Xing Zhao; Jay Ning; Guojie Cheng; Shijie Chen; Gary Zhang; Abhishek Vikram; Bo Su
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Paper Abstract

Despite great effort before design tapeout, there are still some pattern related systematic defects showing up in production, which impact product yield. Through various check points in the production life cycle endeavor is made to detect these defective patterns. It is seen that apart from the known defective patterns, slight variations of polygon sizes and shapes in the known defective patterns also cause yield loss. This complexity is further compounded when interactions among multiple process layers causes the defect. Normally the exact pattern matching techniques cannot detect these variations of the defective patterns. With the currently existing tools in the fab it is a challenge to define the 'sensitive patterns', which are arbitrary variations in the known 'defective patterns'. A design based approach has been successfully experimented on product wafers to detect yield impacting defects that greatly reduces the TAT for hotspot analysis and also provides optimized care area definition to enable high sensitivity wafer inspection. A novel Rule based pattern search technique developed by Anchor Semiconductor has been used to find sensitive patterns in the full chip design. This technique allows GUI based pattern search rule generation like, edge move or edge-to-edge distance range, so that any variations of a particular sensitive pattern can be captured and flagged. Especially the pattern rules involving multiple process layers, like M1-V1-M2, can be defined easily using this technique. Apart from using this novel pattern search technique, design signatures are also extracted around the defect locations in the wafer and used in defect classification. This enhanced defect classification greatly helps in determining most critical defects among the total defect population. The effectiveness of this technique has been established through design to defect correlation and SEM verification. In this paper we will report details of the design based experiments that were successfully run on multiple process layers in production device.

Paper Details

Date Published: 14 March 2012
PDF: 7 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832716 (14 March 2012); doi: 10.1117/12.918068
Show Author Affiliations
Jing Zhang, Semiconductor Manufacturing International Corp. (China)
Qingxiu Xu, Semiconductor Manufacturing International Corp. (China)
Xin Zhang, Semiconductor Manufacturing International Corp. (China)
Xing Zhao, Semiconductor Manufacturing International Corp. (China)
Jay Ning, Semiconductor Manufacturing International Corp. (China)
Guojie Cheng, Anchor Semiconductor, Inc. (China)
Shijie Chen, Anchor Semiconductor, Inc. (China)
Gary Zhang, Anchor Semiconductor, Inc. (China)
Abhishek Vikram, Anchor Semiconductor, Inc. (United States)
Bo Su, Anchor Semiconductor, Inc. (United States)


Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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