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Proceedings Paper

Design compliance for spacer is dielectric (SID) patterning
Author(s): Gerard Luk-Pat; Alex Miloslavsky; Ben Painter; Li Lin; Peter De Bisschop; Kevin Lucas
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Paper Abstract

Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE. This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID. Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.

Paper Details

Date Published: 13 March 2012
PDF: 13 pages
Proc. SPIE 8326, Optical Microlithography XXV, 83260D (13 March 2012); doi: 10.1117/12.917986
Show Author Affiliations
Gerard Luk-Pat, Synopsys, Inc. (United States)
Alex Miloslavsky, Synopsys, Inc. (United States)
Ben Painter, Synopsys, Inc. (United States)
Li Lin, Synopsys, Inc. (United States)
Peter De Bisschop, IMEC (Belgium)
Kevin Lucas, Synopsys, Inc. (United States)

Published in SPIE Proceedings Vol. 8326:
Optical Microlithography XXV
Will Conley, Editor(s)

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