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Proceedings Paper

Transistor architecture impact on wafer inspection
Author(s): Timothy F. Crimmins
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Paper Abstract

Pitch and CD scaling have been the main drivers of wafer inspection (WI) requirements, with tighter pitches and smaller CD's pushing the adoption of inspection tools with greater capabilities. With the introduction of strained silicon, Hi-k / metal gates and tri-gate transistors, integration schemes are playing a prominent role in WI. The present paper explores, through FDTD aerial image simulations, the impact of device integration scheme on WI. Various defect types are simulated for planar gate, planar Hi-k / metal gate and tri-gate transistors and the impact to WI requirements are explored.

Paper Details

Date Published: 4 April 2012
PDF: 8 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83240C (4 April 2012); doi: 10.1117/12.917009
Show Author Affiliations
Timothy F. Crimmins, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)

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