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Proceedings Paper

Electrical design for manufacturability and lithography and stress variability hotspot detection flows at 28nmn
Author(s): Philippe Hurat; Jianhao Zhu; Edward Teoh
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Paper Abstract

Lithography and stress effects cause Layout Dependent Variability (LDV), which results in unexpected and unaccounted timing variations. Because standard cells yield unpredicted timing variation due to context differences, the LDV methodology includes the Cell Context Analysis (CCA) flow that provides designers a comprehensive framework to optimize the design layouts and tune the cell's electrical performance. Conventional static timing analysis tools do not incorporate the electrical impact due to nearby context proximity. The LDV methodology includes an Advanced Timing Analysis (ATA) flow that accounts for the electrical impact of cell contexts, which provides more accurate timing results and identifies new timing violations on critical paths. This paper presents the electrical DFM (eDFM) methodologies developed by GLOBALFOUNDRIES using Cadence LEA (Litho Electrical Analyzer) at 28nm technology node. The paper also discusses about the CCA results for more than 40 contexts of each cell and reports mean delay variations of 3% or more.

Paper Details

Date Published: 15 March 2012
PDF: 8 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832715 (15 March 2012); doi: 10.1117/12.916742
Show Author Affiliations
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Jianhao Zhu, GLOBALFOUNDRIES Singapore (Singapore)
Edward Teoh, GLOBALFOUNDRIES Singapore (Singapore)


Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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