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Proceedings Paper

A novel methodology for triple/multiple-patterning layout decomposition
Author(s): Rani S. Ghaida; Kanak B. Agarwal; Lars W. Liebmann; Sani R. Nassif; Puneet Gupta
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Paper Abstract

Double patterning (DP) in a litho-etch-litho-etch (LELE) process is an attractive technique to scale the K1 factor below 0.25. For dense bidirectional layers such as the first metal layer (M1), however, density scaling with LELE suffers from poor tip-to-tip (T2T) and tip-to-side (T2S) spacing. As a result, triple-patterning (TP) in a LELELE process has emerged as a strong alternative. Because of the use of a third exposure/etch, LELELE can achieve good T2T and T2S scaling as well as improved pitch scaling over LELE in case further scaling is needed. TP layout decomposition, a.k.a. TP coloring, is much more challenging than DP layout decomposition. One of the biggest complexities of TP decomposition is that a stitch can be between different two-mask combinations (i.e. first/second, first/third, second/third) and, consequently, stitches are color-dependent and candidate stitch locations can be determined only during/after coloring. In this paper, we offer a novel methodology for TP layout decomposition. Rather than simplifying the TP stitching problem by using DP candidate stitches only (as in previous works), the methodology leverages TP stitching capability by considering additional candidate stitch locations to give coloring higher flexibility to resolve decomposition conflicts. To deal with TP coloring complexity, the methodology employs multiple DP coloring steps, which leverages existing infrastructure developed for DP layout decomposition. The method was used to decompose bidirectional M1 and M2 layouts at 45nm, 32nm, 22nm, and 14nm nodes. For reasonably dense layouts, the method achieves coloring solutions with no conflicts (or a reasonable number of conflicts solvable with manual legalization). For very dense and irregular M1 layouts, however, the method was unable to reach a conflict-free solution and a large number of conflicts was observed. Hence, layout simplifications for the M1 layer may be unavoidable to enable TP for the M1 layer. Although we apply the method for TP, the method is more general and can be applied for multiple patterning with any number of masks.

Paper Details

Date Published: 14 March 2012
PDF: 8 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270M (14 March 2012); doi: 10.1117/12.916636
Show Author Affiliations
Rani S. Ghaida, Univ. of California, Los Angeles (United States)
Kanak B. Agarwal, IBM Corp. (United States)
Lars W. Liebmann, IBM Corp. (United States)
Sani R. Nassif, IBM Corp. (United States)
Puneet Gupta, Univ. of California, Los Angeles (United States)


Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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