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Proceedings Paper

Variability aware compact model characterization for statistical circuit design optimization
Author(s): Ying Qiao; Kun Qian; Costas J. Spanos
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Paper Abstract

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose an efficient variabilityaware compact model characterization methodology based on the linear propagation of variance. Hierarchical spatial variability patterns of selected compact model parameters are directly calculated from transistor array test structures. This methodology has been implemented and tested using transistor I-V measurements and the EKV-EPFL compact model. Calculation results compare well to full-wafer direct model parameter extractions. Further studies are done on the proper selection of both compact model parameters and electrical measurement metrics used in the method.

Paper Details

Date Published: 15 March 2012
PDF: 9 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270J (15 March 2012); doi: 10.1117/12.916512
Show Author Affiliations
Ying Qiao, Univ. of California, Berkeley (United States)
Kun Qian, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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