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Proceedings Paper

Advanced techniques for design assembly and characterization for the 14nm node with LFD using a black box API
Author(s): Juliann Opitz; Andres Torres; Ioana Graur; Wael Manhawy; Suniti Kanodia; Marwah Shafee; Sarah Mohamed; Ahmed Hassand; Jeanne Bickford
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Paper Abstract

The need to quickly and flexibly characterize the design manufacturability increases as circuit design scales beyond the 22nm node. Improvements in design practices and design software are enabling this process. The use of carefully characterized design subunits (cells) in the general assembly of the chip is one way to ensure that products are optimized for these increasingly difficult lithographic process challenges. Additionally, software for assessing design robustness has been enhanced to deal with ever more complex resolution enhancement techniques. State of the art simulator and verification tool sets provide the necessary step of creating simulation contours and process variability bands upon which various checks can then be performed. The construction of these contours and bands is often hidden from the user as traditional single or double exposure processes of one or two masks are assumed to be used to create the final layout pattern.

Paper Details

Date Published: 14 March 2012
PDF: 10 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832711 (14 March 2012); doi: 10.1117/12.916431
Show Author Affiliations
Juliann Opitz, Mentor Graphics Corp. (United States)
Andres Torres, Mentor Graphics Corp. (United States)
Ioana Graur, IBM Corp. (United States)
Wael Manhawy, Mentor Graphics Corp. (United States)
Suniti Kanodia, Mentor Graphics Corp. (United States)
Marwah Shafee, Mentor Graphics Corp. (Egypt)
Sarah Mohamed, Mentor Graphics Corp. (Egypt)
Ahmed Hassand, Mentor Graphics Corp. (Egypt)
Jeanne Bickford, IBM Corp. (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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