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Proceedings Paper

Replacing design rules in the VLSI design cycle
Author(s): Paul Hurley; Krzysztof Kryszczuk
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Paper Abstract

We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%.

Paper Details

Date Published: 14 March 2012
PDF: 6 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270B (14 March 2012); doi: 10.1117/12.916428
Show Author Affiliations
Paul Hurley, IBM Zürich Research Lab. (Switzerland)
Krzysztof Kryszczuk, IBM Zürich Research Lab. (Switzerland)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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