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Proceedings Paper

CP element based design for 14nm node EBDW high volume manufacturing
Author(s): Takashi Maruyama; Yasuhide Machida; Shinji Sugatani; Hiroshi Takita; Hiromi Hoshino; Toshio Hino; Masaru Ito; Akio Yamada; Tetsuya Iizuka; Satoshi Komatsu; Makoto Ikeda; Kunihiro Asada
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Paper Abstract

We had previously established CP (character projection) based EBDW technology for 65nm and 45nm device production. And recently we have confirmed the resolution of 14nm L&S patterns which meets 14nm and beyond node logic requirement with CP exposure. From these production achievement and resolution potential, with multi-beam EBDW and CP function, MCC [1] could be one of the most promising technologies for future high volume manufacturing if exposure throughput was drastically enhanced. We have set target throughput as 100 WPH to meet HVM (high volume manufacturing) requirement. Our designed parameters to attain 100 WPH for 14nm result in 150 beams, 10cluster, 100 Giga shots/wafer, 250A/cm^2 and 75uC/cm^2. In addition to multi-beam, drastic exposure shot reduction is indispensable to attain 100 WPH for 14nm node. We have aggressively targeted 100 Giga shot count which is equivalent to covering 300mm wafer with 0.8um x 0.8um square fairly large tile. All device circuit blocks should be structured with only CP defined parts and we should trace back to upstream design flow to RTL. We call this methodology "CP element based design". In near future, Litho-Friendly restricted design would be commonly used [3] [4]. Our CP defined tile based regular layout would be highly compatible with these ultra-regular design approaches. The primal design factors are Logic cell, Memory macro and random interconnect. We have established concepts to accomplish high volume production with CP-based EBDW at 14nm technology node.

Paper Details

Date Published: 21 March 2012
PDF: 11 pages
Proc. SPIE 8323, Alternative Lithographic Technologies IV, 832314 (21 March 2012); doi: 10.1117/12.916315
Show Author Affiliations
Takashi Maruyama, e-Shuttle, Inc. (Japan)
Yasuhide Machida, e-Shuttle, Inc. (Japan)
Shinji Sugatani, e-Shuttle, Inc. (Japan)
Hiroshi Takita, Fujitsu Semiconductor Ltd. (Japan)
Hiromi Hoshino, Fujitsu Semiconductor Ltd. (Japan)
Toshio Hino, Fujitsu Semiconductor Ltd. (Japan)
Masaru Ito, Fujitsu Semiconductor Ltd. (Japan)
Akio Yamada, Advantest Corp. (Japan)
Tetsuya Iizuka, The Univ. of Tokyo (Japan)
Satoshi Komatsu, The Univ. of Tokyo (Japan)
Makoto Ikeda, The Univ. of Tokyo (Japan)
Kunihiro Asada, The Univ. of Tokyo (Japan)

Published in SPIE Proceedings Vol. 8323:
Alternative Lithographic Technologies IV
William M. Tong, Editor(s)

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