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Proceedings Paper

Optimization of blended virtual and actual metrology schemes
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Paper Abstract

There are two competing costs that occur in off line semiconductor processing metrology. One is the cost of operating the metrology tool, and the other is the loss in terms of processing cost and yield due to the time lapse between the occurrence and the correction of a process fault. Virtual metrology (VM) is an alternative scheme which takes data produced by the processing tool in real time (e.g. plasma etching data during isolation trench formation) and predicts an outcome of the wafer (e.g. critical dimension of the trench) utilizing an empirical model. Although VM prediction quality is not as good as that of conventional metrology, it produces an immediate, low cost prediction for each wafer going through a process. In real life, we envision that practical metrology schemes will involve a synergistic blend of VM and actual metrology, the latter being used for the needed periodic recalibration of the VM empirical model. In this work, we formulate the costs associated with Type I and Type II errors that result from a blended metrology scheme, and propose a general framework that can be used to quickly lead to the optimal design of such schemes given the characteristics of the process in question. We also explore the effects of a faulty process (by means of mean shift) on the cost analysis.

Paper Details

Date Published: 5 April 2012
PDF: 9 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83241K (5 April 2012); doi: 10.1117/12.916313
Show Author Affiliations
Jae Yeon Claire Baek, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)

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