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Proceedings Paper

Line-pattern collapse mitigation status for EUV at 32nm HP and below
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Paper Abstract

Line pattern collapse (LPC) becomes a critical concern as integrated circuit fabrication continues to advance towards the 22 nm node and below. Tokyo Electron Limited (TEL) has been investigating LPC mitigation methods for many years [1]. These mitigation methods include surfactant rinses to help reduce surface tension and Laplace pressures forces that accompany traditional DIW rinses. However, the ability to explore LPC mitigation techniques at EUV dimensions is experimentally limited by the cost and availability of EUV exposures. With this in mind, TEL has adopted a combined experimental and simulation approach to further explore LPC mitigation methods. Several analytical models have been proposed [2, 3, 4] for a LPC simulation approach. However, the analytical models based on Euler beam theory are limited in the complexity of profile and material assumptions. Euler beam based models are also now questionable because they are outside the beam theory's intended aspect ratio regime [5]. The authors explore the use of finite element models in addition to Euler beam theory based models to understand resist collapse under typical EUV patterning conditions. The versatility of current finite element techniques allows for exploration of resist material property effects, profile and geometry effects, surface versus bulk modulus effects, and rinse and surfactant rinse effects. This paper will discuss pattern-collapse trends and offers critical learning from this simulation approach combined with experimental results from an EUV exposure system and TEL CLEAN TRACK ACTTM 12 platform, utilizing state of the art collapse mitigation methods.

Paper Details

Date Published: 19 March 2012
PDF: 14 pages
Proc. SPIE 8325, Advances in Resist Materials and Processing Technology XXIX, 83250K (19 March 2012); doi: 10.1117/12.916310
Show Author Affiliations
Michael Carcasi, Tokyo Electron America, Inc. (United States)
Derek Bassett, Tokyo Electron America, Inc. (United States)
Wallace Printz, Tokyo Electron America, Inc. (United States)
Shinichiro Kawakami, Tokyo Electron Technology Ctr., America, LLC (United States)
Yuichiro Miyata, Tokyo Electron Kyushu Ltd. (Japan)


Published in SPIE Proceedings Vol. 8325:
Advances in Resist Materials and Processing Technology XXIX
Mark H. Somervell; Thomas I. Wallow, Editor(s)

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