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Proceedings Paper

Local loops for robust inter-layer routing at sub-20 nm nodes
Author(s): Wenbin Huang; Daniel Morris; Neal Lafferty; Lars Liebmann; Kaushik Vaidyanathan; Kafai Lai; Larry Pileggi; Andrzej J. Strojwas
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Paper Abstract

As the metal pitch continues to shrink, it becomes inefficient, if not impossible, to use traditional via redundancy schemes at and below the 14 nm node. Double-cut vias and via bar connections will either block many adjacent routing resources or make it impossible to pattern at these advanced technologies nodes. In this paper we examine a scalable via redundancy strategy based on local loops. We evaluate the yield and timing impact of local loops and use a 14 nm standard cell library and functional block designs to assess the design cost of local loops. Furthermore, lithography contours and process window simulations are used to demonstrate the manufacturability of this structure. With supporting EDA tools and design-technology co-optimization (DTCO), local loops will become an important via redundancy topology at sub-20nm nodes.

Paper Details

Date Published: 14 March 2012
PDF: 9 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270D (14 March 2012); doi: 10.1117/12.916290
Show Author Affiliations
Wenbin Huang, Carnegie Mellon Univ. (United States)
Daniel Morris, Carnegie Mellon Univ. (United States)
Neal Lafferty, IBM Corp. (United States)
Lars Liebmann, IBM Corp. (United States)
Kaushik Vaidyanathan, Carnegie Mellon Univ. (United States)
Kafai Lai, IBM Corp. (United States)
Larry Pileggi, Carnegie Mellon Univ. (United States)
Andrzej J. Strojwas, Carnegie Mellon Univ. (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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