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Proceedings Paper

In-design hierarchical DFM closure for DFM-clean IP
Author(s): Vikas Tripathi; Jayathi Subramanian; Puneet Sharma; Kuang-Han Chen; Bala Kasthuri; Philippe Hurat; Larry Layton
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Paper Abstract

This paper presents the requirements for the Design for Manufacturability (DFM) checks such as lithography, and Chemical and Mechanical Polishing (CMP) at 28nm technology node, and the need to perform these DFM checks, early in the design phase and with minimum overhead. As a result, this reduces the risk of uncovering some DFM issues at the design tape out time when the changes in a design become expensive. Because IP blocks can be targeted to multiple designs, it is a key requirement that the lithography and CMP checks are accurate and designer-friendly and are easily applied at block-level. This paper describes the block-based methodology that allows the IP designers to perform quickly a comprehensive DFM analysis, including lithography and long-range CMP effects. This paper also explains the integration of the DFM checks into the design flow and correlation results between the block and chip-level checks.

Paper Details

Date Published: 14 March 2012
PDF: 8 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270W (14 March 2012); doi: 10.1117/12.916219
Show Author Affiliations
Vikas Tripathi, Freescale Semiconductor India (India)
Jayathi Subramanian, Freescale Semiconductor, Inc. (United States)
Puneet Sharma, Freescale Semiconductor, Inc. (United States)
Kuang-Han Chen, Cadence Design Systems, Inc. (United States)
Bala Kasthuri, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Larry Layton, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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