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Proceedings Paper

Design level variability analysis and parametric yield improvement methodology
Author(s): Reinhard März; Martin Keck
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Paper Abstract

With the transition to the 32/28 nm platform parameter variations of device and circuit parameters are becoming increasingly important for performance, reliability and yield. Based on a sensitivity analysis, the paper compares the impact of lithography and CMP on circuit parameter variations. Coupling capacitances that can be described by geometrical parameters such as line width and thickness impact signal delay, crosstalk noise and power consumption. Variations of these capacitances thus contribute significantly to parametric yield loss. Based on field solver simulations the most critical devices and interconnections can be identified, providing valuable input during the chip design cycle.

Paper Details

Date Published: 14 March 2012
PDF: 7 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270H (14 March 2012); doi: 10.1117/12.916153
Show Author Affiliations
Reinhard März, Intel GmbH (Germany)
Martin Keck, Intel GmbH (Germany)


Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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