Share Email Print

Proceedings Paper

Recess gate process control by using 3D SCD in 3xm vertical DRAM
Author(s): Ming-Feng Kuo; Sheng-Hung Wu; Tien-Hung Lan; Shuang Hsun Chang; Elvis Wang; Houssam Chouaib; Harvey Cheng; Qiang Zhao
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

As DRAM design advances from planar to vertical integration, process control of the recessed gate, generated by etching after patterning in vertical DRAM, is very critical because of the impact on device electrical characteristics and subsequent effect on yield. 3D Scatterometry Critical Dimension (3D SCD) technology is a widely-used metrology approach for process control for leading edge CMOS and DRAM IC manufacturing. In this paper, the latest KLA-Tencor AcuShapeTM modeling software with 3D SCD capability is used in the modeling and solution development, and the SpectraShapeTM 8660 is used for data collection and CD measurement. Recess gate measurements were taken in the active cell area having a non-orthogonal structure. The SCD measurement results were successfully confirmed to correlate well with cross-section Scanning Electron Microscope (X-SEM) and electrical performance data.

Paper Details

Date Published: 3 April 2012
PDF: 7 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83241Z (3 April 2012); doi: 10.1117/12.916143
Show Author Affiliations
Ming-Feng Kuo, Rexchip Electronics Corp. (Taiwan)
Sheng-Hung Wu, Rexchip Electronics Corp. (Taiwan)
Tien-Hung Lan, Rexchip Electronics Corp. (Taiwan)
Shuang Hsun Chang, Rexchip Electronics Corp. (Taiwan)
Elvis Wang, KLA-Tencor Corp. (United States)
Houssam Chouaib, KLA-Tencor Corp. (United States)
Harvey Cheng, KLA-Tencor Corp. (United States)
Qiang Zhao, KLA-Tencor Corp. (United States)

Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)

© SPIE. Terms of Use
Back to Top