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Proceedings Paper

Fast optical proximity correction with timing optimization ready standard cells
Author(s): Yifan Qu; Chun Huat Heng; Arthur Tay; Tong Heng Lee
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Paper Abstract

Resolution enhancement techniques (RET) such as optical proximity correction (OPC) has become an integral part of the fabrication of integrated circuits to maintain the edge placement integrity of the original circuit design. Conventional OPC schemes are usually shape driven and full chip based, resulting in unpredictability in electrical behavior and huge computational effort. To overcome these drawbacks, a new OPC methodology which is electrically driven and based on cell-wise optimization is proposed. Simulation results when compared to conventional OPC approaches in the literature demonstrate better timing accuracy with reduced mask cost. Depending of the circuit test-set, an average run-time improvement between 3 to 8 times is achieved for circuit size with 100 - 400 cells. Further improvements can be obtained by adopting a hybrid approach by only optimizing the timing performance of critical paths. For the hybrid approach, better timing accuracy can be achieved while incurring little penalty on mask cost.

Paper Details

Date Published: 14 March 2012
PDF: 11 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832714 (14 March 2012); doi: 10.1117/12.916124
Show Author Affiliations
Yifan Qu, National Univ. of Singapore (Singapore)
Chun Huat Heng, National Univ. of Singapore (Singapore)
Arthur Tay, National Univ. of Singapore (Singapore)
Tong Heng Lee, National Univ. of Singapore (Singapore)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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