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Proceedings Paper

How to minimize CD variation and overlay degradation induced by film stress
Author(s): Woo-Yung Jung; Yong-Hyun Lim; Shin-Ae Park; Sang-Joon Ahn; Ji-Hyun Lee; Jung-A Yoo; Seung-Ho Pyi; Jin-Woong Kim
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Paper Abstract

It is getting harder to minimize feature size to satisfy bit growth requirement. 3D NAND flash memory has been developed to meet bit growth requirement without shrinking feature size. To increase the number of memory cells per unit area without shrinking feature size, we should increase the number of stacked film layers which finally become memory cells. Wafer warpage is induced by the stress between film and wafer. Both of film stress and wafer warpage increase in proportion to stacked film layers, and the increase of wafer warpage makes CD uniformity worse. Overlay degradation has no relation with wafer warpage, but has indirect relation with film stress. Wafer deformation in film deposition chamber is the source of overlay degradation. In this paper, we study the reasons why CD uniformity and overlay accuracy are affected by film stress, and suggest the methods which keep CD uniformity and overlay accuracy safe without additional processes.

Paper Details

Date Published: 5 April 2012
PDF: 8 pages
Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 83242L (5 April 2012); doi: 10.1117/12.916035
Show Author Affiliations
Woo-Yung Jung, Hynix Semiconductor Inc. (Korea, Republic of)
Yong-Hyun Lim, Hynix Semiconductor Inc. (Korea, Republic of)
Shin-Ae Park, Hynix Semiconductor Inc. (Korea, Republic of)
Sang-Joon Ahn, Hynix Semiconductor Inc. (Korea, Republic of)
Ji-Hyun Lee, Hynix Semiconductor Inc. (Korea, Republic of)
Jung-A Yoo, Hynix Semiconductor Inc. (Korea, Republic of)
Seung-Ho Pyi, Hynix Semiconductor Inc. (Korea, Republic of)
Jin-Woong Kim, Hynix Semiconductor Inc. (Korea, Republic of)


Published in SPIE Proceedings Vol. 8324:
Metrology, Inspection, and Process Control for Microlithography XXVI
Alexander Starikov, Editor(s)

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