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Proceedings Paper

The complexity of fill at 28nm and beyond
Author(s): Norma Rodriguez; Jie Yang; Bill Graupp; Jeff Wilson; Eugene Anikin
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Paper Abstract

The history of dummy fill in semiconductor design goes back many generations of technology development. From its start with planarization requirements, fill needs have expanded across many wafer process manufacturing steps. They include lithography, etch, deposition, surface anneal, and device performance with stress analysis. Modern EDA tools have advanced to automatically place dummy shapes to meet these new requirements. These include placing multi-layer cell constructs, and multi-layer analysis during placement. New fill requirements have affected downstream flows such as extraction and timing analysis, physical verification, and RET flows. Further enhancements to fill tools and flows are under development to meet the total DFM needs for the next generations of chips.

Paper Details

Date Published: 14 March 2012
PDF: 6 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270Q (14 March 2012); doi: 10.1117/12.916011
Show Author Affiliations
Norma Rodriguez, Advanced Micro Devices, Inc. (United States)
Jie Yang, Advanced Micro Devices, Inc. (United States)
Bill Graupp, Mentor Graphics Corp. (United States)
Jeff Wilson, Mentor Graphics Corp. (United States)
Eugene Anikin, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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