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Proceedings Paper

Automated yield enhancements implementation on full 28nm chip: challenges and statistics
Author(s): Shobhit Malik; Sriram Madhavan; Piyush Pathak; Luigi Capodieci; Ramy Fathy; Ahmad Abdulghany
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Paper Abstract

This paper shares the details of the Yield Enhancements that were done at 28nm full chip level sharing the complexity involved in implementing such a flow and then the verification challenges involved , e.g., at mask data preparation. We discuss and present the algorithm used to measure the efficiency of the tool, explaining why we used this algorithm while sharing some alternate algorithms possible. We also share the detailed statistics regarding run time, machine resource, data size, polygon counts etc. We also present good techniques used by us for efficient flow management involved in large complex 28nm chips.

Paper Details

Date Published: 14 March 2012
PDF: 9 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 83270X (14 March 2012); doi: 10.1117/12.915920
Show Author Affiliations
Shobhit Malik, GLOBALFOUNDRIES Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)
Piyush Pathak, GLOBALFOUNDRIES Inc. (United States)
Luigi Capodieci, GLOBALFOUNDRIES Inc. (United States)
Ramy Fathy, Mentor Graphics Corp. (United States)
Ahmad Abdulghany, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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