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Proceedings Paper

Applicability of double-patterning process for fine-hole patterns
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Paper Abstract

Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device, because SADP can fabricate fine periodical line pattern more easily than pitch-split type DP. Furthermore, SADP can mitigate overlay accuracy such like pith-split type DP needed. The remarkable feature of SADP process is the adoption of a SiO2 film that can be deposited at extremely low temperatures for spacer formation. SADP and this deposition process also produce wide applicability to density multiplication on hole pattern. In our previous study, hole pattern fabrication below 40nmhp was examined. 30nm hp hole pattern was viable with single 193-immersion exposure successfully with our newly developed process scheme named EKB, and ultimate down-scaling on hole pattern, achieved to 20nm hp, was introduced utilizing cross-SADP[1][2]. In logic device manufacturing, pattern layout is getting to single directional, tabbed Gridded design rule (GDR) for the mitigation of various lithographic issues. Although Self-aligned type DP for hole pattern can describe periodical layout, it is really enabled for future simplified pattern layout. In this paper, successful demonstration results would be introduced in process simplification, process extendibility, CD controllability and further downward scaling.

Paper Details

Date Published: 19 March 2012
PDF: 6 pages
Proc. SPIE 8325, Advances in Resist Materials and Processing Technology XXIX, 832526 (19 March 2012); doi: 10.1117/12.915818
Show Author Affiliations
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)

Published in SPIE Proceedings Vol. 8325:
Advances in Resist Materials and Processing Technology XXIX
Mark H. Somervell; Thomas I. Wallow, Editor(s)

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