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Proceedings Paper

Consideration of correlativity between litho and etching shape
Author(s): Ryoichi Matsuoka; Hiroaki Mito; Shinichi Shinoda; Yasutaka Toyoda
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Paper Abstract

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

Paper Details

Date Published: 15 March 2012
PDF: 10 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832710 (15 March 2012); doi: 10.1117/12.915785
Show Author Affiliations
Ryoichi Matsuoka, Hitachi High-Technologies Corp. (Japan)
Hiroaki Mito, Hitachi High-Technologies Corp. (Japan)
Shinichi Shinoda, Hitachi Research Lab., Hitachi Ltd. (Japan)
Yasutaka Toyoda, Hitachi Research Lab., Hitachi Ltd. (Japan)


Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)

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