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Design friendly double patterningFormat | Member Price | Non-Member Price |
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Paper Abstract
Double patterning using 193nm immersion has been adapted as the solution to enable 2x nm technology nodes until the
arrival of EUV tools. As a result the past few years have seen a huge effort in creating double patterning friendly design
flows. These flows have so far proposed a combination of decomposition rules at cell level and/or at placement level as
well as sophisticated decomposition tools with varying density, design iteration and decomposition complexity penalties.
What is more, designers have to familiarize themselves with double patterning challenges and decomposition tools. In
this paper an alternative approach is presented that allows the development of dense standard cells with minimal impact
on design flow due to double patterning. A real case study is done on 20nm node first metal layer where standard cells
are designed without considering decomposition restrictions. The resulting layout is carefully studied in order to
establish decomposition or color rules that can map the layout into two masks required for double patterning but without
the need of complex coloring algorithms. Since the rules are derived from a decomposition unaware design they do not
in return impose heavy restrictions on the design at the cell or placement level and show substantial density gains
compared to previously proposed methods. Other key advantages are a simplified design flow without complex
decomposition tools that can generate a faster time to market solution all at the same time keeping designers isolated
from the challenges of the double patterning. The derived design rules highlight process development path required for
design driven manufacturing.
Paper Details
Date Published: 14 March 2012
PDF: 12 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832707 (14 March 2012); doi: 10.1117/12.915713
Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)
PDF: 12 pages
Proc. SPIE 8327, Design for Manufacturability through Design-Process Integration VI, 832707 (14 March 2012); doi: 10.1117/12.915713
Show Author Affiliations
Emek Yesilada, STMicroelectronics (France)
Published in SPIE Proceedings Vol. 8327:
Design for Manufacturability through Design-Process Integration VI
Mark E. Mason, Editor(s)
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