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Proceedings Paper

Hardware accelerator design for change detection in smart camera
Author(s): Sanjay Singh; Srinivasa Murali Dunga; Ravi Saini; A. S. Mandal; Chandra Shekhar; Santanu Chaudhury; Anil Vohra
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Paper Abstract

Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

Paper Details

Date Published: 1 October 2011
PDF: 5 pages
Proc. SPIE 8285, International Conference on Graphic and Image Processing (ICGIP 2011), 82852T (1 October 2011); doi: 10.1117/12.913591
Show Author Affiliations
Sanjay Singh, Central Electronics Engineering Research Institute (India)
Srinivasa Murali Dunga, Central Electronics Engineering Research Institute (India)
Ravi Saini, Central Electronics Engineering Research Institute (India)
A. S. Mandal, Central Electronics Engineering Research Institute (India)
Chandra Shekhar, Central Electronics Engineering Research Institute (India)
Santanu Chaudhury, Indian Institute of Technology Delhi (India)
Anil Vohra, Kurukshetra Univ. (India)


Published in SPIE Proceedings Vol. 8285:
International Conference on Graphic and Image Processing (ICGIP 2011)
Yi Xie; Yanjun Zheng, Editor(s)

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