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Proceedings Paper

Hardware-software partitioning for the design of system on chip by neural network optimization method
Author(s): Zhongliang Pan; Wei Li; Qingyi Shao; Ling Chen
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Paper Abstract

In the design procedure of system on chip (SoC), it is needed to make use of hardware-software co-design technique owing to the great complexity of SoC. One of main steps in hardware-software co-design is how to carry out the partitioning of a system into hardware and software components. The efficient approaches for hardware-software partitioning can achieve good system performance, which is superior to the techniques that use software only or use hardware only. In this paper, a method based on neural networks is presented for the hardware-software partitioning of system on chip. The discrete Hopfield neural networks corresponding to the problem of hardware-software partitioning is built, the states of neural neurons are able to represent whether the required components or functionalities are to be implemented in hardware or software. An algorithm based on the principle of simulated annealing is designed, which can be used to compute the minimal energy states of neural networks, therefore the optimal partitioning schemes are obtained. The experimental results show that the hardware-software partitioning method proposed in this paper can obtain the near optimal partitioning for a lot of example circuits.

Paper Details

Date Published: 15 November 2011
PDF: 6 pages
Proc. SPIE 8321, Seventh International Symposium on Precision Engineering Measurements and Instrumentation, 83211T (15 November 2011); doi: 10.1117/12.904816
Show Author Affiliations
Zhongliang Pan, South China Normal Univ. (China)
Wei Li, South China Normal Univ. (China)
Qingyi Shao, South China Normal Univ. (China)
Ling Chen, South China Normal Univ. (China)


Published in SPIE Proceedings Vol. 8321:
Seventh International Symposium on Precision Engineering Measurements and Instrumentation
Kuang-Chao Fan; Man Song; Rong-Sheng Lu, Editor(s)

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