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Proceedings Paper

A co-design method for parallel image processing accelerator based on DSP and FPGA
Author(s): Ze Wang; Kaijian Weng; Zhao Cheng; Luxin Yan; Jing Guan
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Paper Abstract

In this paper, we present a co-design method for parallel image processing accelerator based on DSP and FPGA. DSP is used as application and operation subsystem to execute the complex operations, and in which the algorithms are resolving into commands. FPGA is used as co-processing subsystem for regular data-parallel processing, and operation commands and image data are transmitted to FPGA for processing acceleration. A series of experiments have been carried out, and up to a half or three quarter time is saved which supports that the proposed accelerator will consume less time and get better performance than the traditional systems.

Paper Details

Date Published: 5 December 2011
PDF: 6 pages
Proc. SPIE 8005, MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing, 800506 (5 December 2011); doi: 10.1117/12.901244
Show Author Affiliations
Ze Wang, Huazhong Univ. of Science and Technology (China)
Kaijian Weng, Huazhong Univ. of Science and Technology (China)
Zhao Cheng, Institute of Manned Space System Engineering (China)
Luxin Yan, Huazhong Univ. of Science and Technology (China)
Jing Guan, Huazhong Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 8005:
MIPPR 2011: Parallel Processing of Images and Optimization and Medical Imaging Processing
Faxiong Zhang; Faxiong Zhang, Editor(s)

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