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Proceedings Paper

SEU mitigation strategies for SRAM-based FPGA
Author(s): Pei Luo; Jian Zhang
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Paper Abstract

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

Paper Details

Date Published: 15 August 2011
PDF: 10 pages
Proc. SPIE 8196, International Symposium on Photoelectronic Detection and Imaging 2011: Space Exploration Technologies and Applications, 81960N (15 August 2011); doi: 10.1117/12.899744
Show Author Affiliations
Pei Luo, Ctr. for Space Science and Applied Research (China)
Jian Zhang, Ctr. for Space Science and Applied Research (China)


Published in SPIE Proceedings Vol. 8196:
International Symposium on Photoelectronic Detection and Imaging 2011: Space Exploration Technologies and Applications
John C. Zarnecki; Carl A. Nardell; Rong Shu; Jianfeng Yang; Yunhua Zhang, Editor(s)

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