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Proceedings Paper

Collaborative research on emerging technologies and design
Author(s): Andrew R. Neureuther; Juliet Rubinstein; Marshal Miller; Kenji Yamazoe; Eric Chin; Cooper Levy; Lynn Wang; Nuo Xu; Costas Spanos; Kun Qian; Kameshwar Poolla; Justin Ghan; Anand Subramanian; Tsu-Jae King Liu; Xin Sun; Kwangok Jeong; Puneet Gupta; Abde Kaqalwalla; Rani Ghaida; Tuck Boon Chan
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Paper Abstract

Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits are described. These results are from multi-discipline, collaborative university-industry research and emphasize anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes design and testing electronic monitors in silicon at 45 nm and fast-CAD tools to identify systematic variations for entire chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow characterization.

Paper Details

Date Published: 19 May 2011
PDF: 7 pages
Proc. SPIE 8081, Photomask and Next-Generation Lithography Mask Technology XVIII, 80810N (19 May 2011); doi: 10.1117/12.899394
Show Author Affiliations
Andrew R. Neureuther, Univ. of California, Berkeley (United States)
Juliet Rubinstein, Univ. of California, Berkeley (United States)
Marshal Miller, Univ. of California, Berkeley (United States)
Kenji Yamazoe, Univ. of California, Berkeley (United States)
Eric Chin, Univ. of California, Berkeley (United States)
Cooper Levy, Univ. of California, Berkeley (United States)
Lynn Wang, Univ. of California, Berkeley (United States)
Nuo Xu, Univ. of California, Berkeley (United States)
Costas Spanos, Univ. of California, Berkeley (United States)
Kun Qian, Univ. of California, Berkeley (United States)
Kameshwar Poolla, Univ. of California, Berkeley (United States)
Justin Ghan, Univ. of California, Berkeley (United States)
Anand Subramanian, Univ. of California, Berkeley (United States)
Tsu-Jae King Liu, Univ. of California, Berkeley (United States)
Xin Sun, Univ. of California, Berkeley (United States)
Kwangok Jeong, Univ. of California, San Diego (United States)
Puneet Gupta, Univ. of California, Los Angeles (United States)
Abde Kaqalwalla, Univ. of California, Los Angeles (United States)
Rani Ghaida, Univ. of California, Los Angeles (United States)
Tuck Boon Chan, Univ. of California, Los Angeles (United States)


Published in SPIE Proceedings Vol. 8081:
Photomask and Next-Generation Lithography Mask Technology XVIII
Toshio Konishi, Editor(s)

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