Share Email Print
cover

Proceedings Paper

Design of 300 frames per second 16-port CCD video processing circuit
Author(s): Shao-hua Yang; Ming-an Guo; Bin-kang Li; Jing-tao Xia; Qunshu Wang
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

It is hard to achieve the speed of hundreds frames per second in high resolution charge coupled device (CCD) cameras, because the pixels' charge must be read out one by one in serial mode, this cost a lot of time. The multiple-port CCD technology is a new efficiency way to realize high frame rate high resolution solid state imaging systems. The pixel charge is read out from a multiple-port CCD through several ports in parallel mode, witch decrease the reading time of the CCD. But it is hard for the multiple-port CCDs' video processing circuit design, and the real time high speed image data acquisition is also a knotty problem. A 16-port high frame rate CCD video processing circuit based on Complex Programmable Logic Device (CPLD) and VSP5010 has been developed around a specialized back illuminated, 512 x 512 pixels, 400fps (frames per second) frame transfer CCD sensor from Sarnoff Ltd. A CPLD is used to produce high precision sample clock and timing, and the high accurate CCD video voltage sample is achieved with Correlated Double Sampling (CDS) technology. 8 chips of VSP5010 with CDS function is adopted to achieve sample and digitize CCD analog signal into 12 bit digital image data. Thus the 16 analog CCD output was digitized into 192 bit 6.67MHz parallel digital image data. Then CPLD and Time Division Multiplexing (TDM) technology are used to encode the 192 bit wide data into two 640MHz serial data and transmitted to remote data acquisition module via two fibers. The acquisition module decodes the serial data into original image data and stores the data into a frame cache, and then the software reads the data from the frame cache based on USB2.0 technology and stores the data in a hard disk. The digital image data with 12bit per pixel was collected and displayed with system software. The results show that the 16-por 300fps CCD output signals could be digitized and transmitted with the video processing circuit, and the remote data acquisition has been realized.

Paper Details

Date Published: 18 August 2011
PDF: 6 pages
Proc. SPIE 8194, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Imaging Detectors and Applications, 81940L (18 August 2011); doi: 10.1117/12.898908
Show Author Affiliations
Shao-hua Yang, Northwest Institute of Nuclear Technology (China)
Ming-an Guo, Northwest Institute of Nuclear Technology (China)
Bin-kang Li, Northwest Institute of Nuclear Technology (China)
Jing-tao Xia, Northwest Institute of Nuclear Technology (China)
Qunshu Wang, Northwest Institute of Nuclear Technology (China)


Published in SPIE Proceedings Vol. 8194:
International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Imaging Detectors and Applications
Makoto Ikeda; Nanjian Wu; Guangjun Zhang; Kecong Ai, Editor(s)

© SPIE. Terms of Use
Back to Top