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Proceedings Paper

Low-power, high-speed FFT processor for MB-OFDM UWB application
Author(s): Guixuan Liang; Danping He; Eduardo de la Torre; Teresa Riesgo
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Paper Abstract

This paper presents a low-power, high-speed 4-data-path 128-point mixed-radix (radix-2 & radix-22) FFT processor for MB-OFDM Ultra-WideBand (UWB) systems. The processor employs the single-path delay feedback (SDF) pipelined structure for the proposed algorithm, it uses substructure-sharing multiplication units and shift-add structure other than traditional complex multipliers. Furthermore, the word lengths are properly chosen, thus the hardware costs and power consumption of the proposed FFT processor are efficiently reduced. The proposed FFT processor is verified and synthesized by using 0.13 μm CMOS technology with a supply voltage of 1.32 V. The implementation results indicate that the proposed 128-point mixed-radix FFT architecture supports a throughput rate of 1Gsample/s with lower power consumption in comparison to existing 128-point FFT architectures.

Paper Details

Date Published: 3 May 2011
PDF: 10 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 80670E (3 May 2011); doi: 10.1117/12.890303
Show Author Affiliations
Guixuan Liang, Univ. Politécnica de Madrid (Spain)
Danping He, Univ. Politécnica de Madrid (Spain)
Eduardo de la Torre, Univ. Politécnica de Madrid (Spain)
Teresa Riesgo, Univ. Politécnica de Madrid (Spain)


Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)

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