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Proceedings Paper

40Gbit/s interface conversion circuit for 40GbE, STM-256/OC-768 and OTU3 serial signal transport
Author(s): Shigeki Aisawa; Masahito Tomizawa
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Paper Abstract

We use a 65nm CMOS process technology to develop 40Gbit/s interface conversion prototype circuits for 40GbE, STM- 256/OC-768 and OTU3 tri-rate serial signal transport. For the first time, interface conversion functions from SFI-5.1 to SFI-5.2/XLAUI are demonstrated on a 16:4 MUX prototype chip, and from SFI-5.2/XLAUI to SFI-5.1 on a 4:16 DEMUX prototype chip. The 16:4 MUX and 4:16 DEMUX prototype chips show excellent jitter performance and consume 1.6 and 1.7 W, respectively.

Paper Details

Date Published: 18 February 2011
PDF: 6 pages
Proc. SPIE 7988, Optical Transmission Systems, Switching, and Subsystems VIII, 79880L (18 February 2011); doi: 10.1117/12.888248
Show Author Affiliations
Shigeki Aisawa, NTT Network Innovation Labs. (Japan)
Photonics Electronics Technology Research Association (Japan)
Masahito Tomizawa, NTT Network Innovation Labs. (Japan)
Photonics Electronics Technology Research Association (Japan)


Published in SPIE Proceedings Vol. 7988:
Optical Transmission Systems, Switching, and Subsystems VIII
Yikai Su; Ernesto Ciaramella; Xiang Liu; Naoya Wada, Editor(s)

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