Share Email Print
cover

Proceedings Paper

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs
Author(s): A. Otero; M. Llinás; M. L. Lombardo; Jorge Portilla; E. de la Torre; T. Riesgo
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Modern FPGAs with run-time reconfiguration allow the implementation of complex systems offering both the flexibility of software-based solutions combined with the performance of hardware. This combination of characteristics, together with the development of new specific methodologies, make feasible to reach new points of the system design space, and make embedded systems built on these platforms acquire more and more importance. However, the practical exploitation of this technique in fields that traditionally have relied on resource restricted embedded systems, is mainly limited by strict power consumption requirements, the cost and the high dependence of DPR techniques with the specific features of the device technology underneath. In this work, we tackle the previously reported problems, designing a reconfigurable platform based on the low-cost and low-power consuming Spartan-6 FPGA family. The full process to develop the platform will be detailed in the paper from scratch. In addition, the implementation of the reconfiguration mechanism, including two profiles, is reported. The first profile is a low-area and low-speed reconfiguration engine based mainly on software functions running on the embedded processor, while the other one is a hardware version of the same engine, implemented in the FPGA logic. This reconfiguration hardware block has been originally designed to the Virtex-5 family, and its porting process will be also described in this work, facing the interoperability problem among different families.

Paper Details

Date Published: 3 May 2011
PDF: 13 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 806706 (3 May 2011); doi: 10.1117/12.887498
Show Author Affiliations
A. Otero, Univ. Politécnica de Madrid (Spain)
M. Llinás, Univ. Politécnica de Madrid (Spain)
M. L. Lombardo, Univ. Politécnica de Madrid (Spain)
Jorge Portilla, Univ. Politécnica de Madrid (Spain)
E. de la Torre, Univ. Politécnica de Madrid (Spain)
T. Riesgo, Univ. Politécnica de Madrid (Spain)


Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)

© SPIE. Terms of Use
Back to Top