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Proceedings Paper

Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems
Author(s): Rubén Salvador; Alberto Vidal; Félix Moreno; Teresa Riesgo; Lukáš Sekanina
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Paper Abstract

A generic bio-inspired adaptive architecture for image compression suitable to be implemented in embedded systems is presented. The architecture allows the system to be tuned during its calibration phase. An evolutionary algorithm is responsible of making the system evolve towards the required performance. A prototype has been implemented in a Xilinx Virtex-5 FPGA featuring an adaptive wavelet transform core directed at improving image compression for specific types of images. An Evolution Strategy has been chosen as the search algorithm and its typical genetic operators adapted to allow for a hardware friendly implementation. HW/SW partitioning issues are also considered after a high level description of the algorithm is profiled which validates the proposed resource allocation in the device fabric. To check the robustness of the system and its adaptation capabilities, different types of images have been selected as validation patterns. A direct application of such a system is its deployment in an unknown environment during design time, letting the calibration phase adjust the system parameters so that it performs efcient image compression. Also, this prototype implementation may serve as an accelerator for the automatic design of evolved transform coefficients which are later on synthesized and implemented in a non-adaptive system in the final implementation device, whether it is a HW or SW based computing device. The architecture has been built in a modular way so that it can be easily extended to adapt other types of image processing cores. Details on this pluggable component point of view are also given in the paper.

Paper Details

Date Published: 3 May 2011
PDF: 13 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 806704 (3 May 2011); doi: 10.1117/12.887123
Show Author Affiliations
Rubén Salvador, Univ. Politécnica de Madrid (Spain)
Alberto Vidal, Univ. Politécnica de Madrid (Spain)
Félix Moreno, Univ. Politécnica de Madrid (Spain)
Teresa Riesgo, Univ. Politécnica de Madrid (Spain)
Lukáš Sekanina, Brno Univ. of Technology (Czech Republic)


Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)

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