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Proceedings Paper

Self-repairing SRAM architecture to mitigate the inter-die process variations at 65nm technology
Author(s): Sumit Kansal; Marco Lanuzza; Pasquale Corsonello
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Paper Abstract

With aggressive scaling, one of the major barriers that CMOS technology faces is the increasing process variations. The variations in process parameters not only affect the performance of the devices but also degrade the parametric yield of the circuits. Adaptive repairing techniques like adaptive body bias were proved to be effective to mitigate variations in the process parameters. In this paper, we evaluate the use of zone based self-repairing techniques to mitigate the impact of process variations on SRAM cells. Two different techniques were experimented and analyzed through extensive Monte Carlo simulations and exploiting a commercial 65nm technology. Obtained results demonstrate that improvements up to 35.7% in variability factor for leakage power and up to 22.3% in Design Margin for leakage power can be achieved by using the suggested approach.

Paper Details

Date Published: 3 May 2011
PDF: 7 pages
Proc. SPIE 8067, VLSI Circuits and Systems V, 80670X (3 May 2011); doi: 10.1117/12.886873
Show Author Affiliations
Sumit Kansal, Univ. of Calabria (Italy)
Marco Lanuzza, Univ. of Calabria (Italy)
Pasquale Corsonello, Univ. of Calabria (Italy)


Published in SPIE Proceedings Vol. 8067:
VLSI Circuits and Systems V
Teresa Riesgo; Eduardo de la Torre-Arnanz, Editor(s)

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