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Proceedings Paper

Parallel design patterns for a low-power, software-defined compressed video encoder
Author(s): Michael W. Bruns; Martin A. Hunt; Durga Prasad; Nageswara Rao Gunupudi; Sekar Sonachalam
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Paper Abstract

Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork processor device.

Paper Details

Date Published: 26 May 2011
PDF: 10 pages
Proc. SPIE 8063, Mobile Multimedia/Image Processing, Security, and Applications 2011, 80630E (26 May 2011); doi: 10.1117/12.884422
Show Author Affiliations
Michael W. Bruns, Coherent Logix, Inc. (United States)
Martin A. Hunt, Coherent Logix, Inc. (United States)
Durga Prasad, Parallel Prisms (United States)
Nageswara Rao Gunupudi, Parallel Prisms (United States)
Sekar Sonachalam, Parallel Prisms (United States)

Published in SPIE Proceedings Vol. 8063:
Mobile Multimedia/Image Processing, Security, and Applications 2011
Sos S. Agaian; Sabah A. Jassim; Yingzi Du, Editor(s)

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