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Proceedings Paper

Scaling trends of single-photon avalanche diode arrays in nanometer CMOS technology
Author(s): Justin A. Richardson; Eric A. G. Webster; Lindsay A. Grant; Robert K. Henderson
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Paper Abstract

A family of scaleable single photon avalanche diode (SPAD) structures in 130nm and 90nm CMOS is presented. Performance trends such as dark count rate (DCR), jitter and breakdown voltage are studied versus active diameter for devices ranging from 32μm down to 2μm. To address pixel pitch we introduce a shared buried n-well approach allowing compact arrays containing both NMOS-transistor readout circuitry and SPAD devices. A pixel pitch of 5μm has been achieved in 90nm CMOS technology, offering the potential for future megapixel single photon image sensors.

Paper Details

Date Published: 12 May 2011
PDF: 8 pages
Proc. SPIE 8033, Advanced Photon Counting Techniques V, 80330B (12 May 2011); doi: 10.1117/12.884097
Show Author Affiliations
Justin A. Richardson, The Univ. of Edinburgh (United Kingdom)
Dialog Semiconductor (UK) Ltd. (United Kingdom)
Eric A. G. Webster, The Univ. of Edinburgh (United Kingdom)
Lindsay A. Grant, STMicroelectronics (R&D) Ltd. (United Kingdom)
Robert K. Henderson, The Univ. of Edinburgh (United Kingdom)


Published in SPIE Proceedings Vol. 8033:
Advanced Photon Counting Techniques V
Mark A. Itzler; Joe C. Campbell, Editor(s)

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