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Proceedings Paper

Nanoimprint lithography for semiconductor devices and future patterning innovation
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Paper Abstract

Nanoimprint lithography (NIL) has been expected as a low cost lithography solution as well as pattern shrinking capability with superior Critical Dimension (CD) uniformity for several years. However, NIL had been considered having difficulty to be established as mass-production technology, unless the challenge of defectivity control is overcome. The defects of NIL are classified into the non-fill defect, the template defect, and the plug defect. In order to reduce these defects, establishment of the technical infrastructures is important with the innovations of equipment, material, and template technologies. Recently, the investment to lithography becomes heavier burden for a semiconductor device maker, as lithography technology has been more difficult for further pattern shrinking. Therefore, expectation of NIL realization has emerged again. This paper describes current NIL technical status and refers to a future NIL patterning innovation such as a desktop lithography.

Paper Details

Date Published: 17 March 2011
PDF: 6 pages
Proc. SPIE 7970, Alternative Lithographic Technologies III, 797003 (17 March 2011); doi: 10.1117/12.882940
Show Author Affiliations
Tatsuhiko Higashiki, Toshiba Corp. (Japan)
Tetsuro Nakasugi, Toshiba Corp. (Japan)
Ikuo Yoneda, Toshiba Corp. (Japan)


Published in SPIE Proceedings Vol. 7970:
Alternative Lithographic Technologies III
Daniel J. C. Herr, Editor(s)

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