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Proceedings Paper

Enhancing fullchip ILT mask synthesis capability for IC manufacturability
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Paper Abstract

It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh[1][2] thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including: DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask. Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors responsible for their differences include composition of the cost function that is minimized, constraints applied during optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.

Paper Details

Date Published: 23 March 2011
PDF: 8 pages
Proc. SPIE 7973, Optical Microlithography XXIV, 79731C (23 March 2011); doi: 10.1117/12.882814
Show Author Affiliations
Thomas Cecil, Luminescent Technologies, Inc. (United States)
Chris Ashton, Luminescent Technologies, Inc. (United States)
David Irby, Luminescent Technologies, Inc. (United States)
Lan Luan, Luminescent Technologies, Inc. (United States)
D. H. Son, Luminescent Technologies, Inc. (United States)
Guangming Xiao, Luminescent Technologies, Inc. (United States)
Xin Zhou, Luminescent Technologies, Inc. (United States)
David Kim, Luminescent Technologies, Inc. (United States)
Bob Gleason, Luminescent Technologies, Inc. (United States)
H. J. Lee, Samsung Electronics (Korea, Republic of)
W. J. Sim, Samsung Electronics (Korea, Republic of)
M. J. Hong, Samsung Electronics (Korea, Republic of)
S. G. Jung, Samsung Electronics (Korea, Republic of)
S. S. Suh, Samsung Electronics (Korea, Republic of)
S. W. Lee, Samsung Electronics (Korea, Republic of)

Published in SPIE Proceedings Vol. 7973:
Optical Microlithography XXIV
Mircea V. Dusa, Editor(s)

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