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Proceedings Paper

Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs
Author(s): Philippe Hurat; Rasit O. Topaloglu; Ramez Nachman; Piyush Pathak; Jac Condella; Sriram Madhavan; Luigi Capodieci
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Paper Abstract

We identify most recent sources of transistor layout dependent effects (LDE) such as stress, lithography, and well proximity effects (WPE), and outline modeling and analysis methods for 28 nm. These methods apply to custom layout, standard cell designs, and context-aware post-route analysis. We show how IC design teams can use a model-based approach to quantify and analyze variability induced by LDE. We reduce the need for guard-bands that negate the performance advantages that stress brings to advanced process technologies.

Paper Details

Date Published: 4 April 2011
PDF: 13 pages
Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797412 (4 April 2011); doi: 10.1117/12.882508
Show Author Affiliations
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Rasit O. Topaloglu, GLOBALFOUNDRIES Inc. (United States)
Ramez Nachman, Cadence Design Systems, Inc. (United States)
Piyush Pathak, GLOBALFOUNDRIES Inc. (United States)
Jac Condella, Cadence Design Systems, Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)
Luigi Capodieci, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 7974:
Design for Manufacturability through Design-Process Integration V
Michael L. Rieger, Editor(s)

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